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ELEC 451 Digital Integrated Circuit Engineering Units: 3.25
Review of MOS transistor structure and operation; overview of wafer processing and device implementation, layout and design rules. CMOS gate design; static and dynamic logic; modelling of transients and delays. Clocked circuits; interconnect effects, and I/O. Memory and programmable logic arrays. Technology scaling effects; design styles and flow.
NOT OFFERED 2024-2025
(Lec: 3, Lab: 0.25, Tut: 0)
NOT OFFERED 2024-2025
(Lec: 3, Lab: 0.25, Tut: 0)
Offering Term: F
CEAB Units:
Mathematics 0
Natural Sciences 0
Complementary Studies 0
Engineering Science 21
Engineering Design 18
Offering Faculty: Smith Engineering
Course Learning Outcomes:
- Describe the steps of integrated-circuit fabrication processes to form NMOS/PMOS transistors and interconnections using polysilicon and metal.
- Describe robust CMOS circuit implementation of flip-flop behavior and relevant considerations for clock signals to ensure reliable operation.
- Describe cell, sense-amplifier, and address-decoding circuits for implementation of CMOS-based memory arrays.
- Develop a standard-cell physical layout for a schematic CMOS circuit representation.
- Characterize the parasitic and load capacitances for a CMOS circuit, and use that characterization to estimate delays for switching behavior.
- Design static and dynamic CMOS circuits in schematic representation to implement combinational logic functions.