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ELEC 374  Digital Systems Engineering  Units: 4.25  
High-performance logic design for arithmetic circuits; memory system designs based on static and dynamic RAMs; computer bus protocols and standard I/O interfaces; mass storage devices; hardware description languages (VHDL, Verilog); fault testing, design for testability, built-in self-test, memory testing, and boundary-scan architectures; asynchronous sequential circuit design; introduction to GPU architectures and GPU computing. The course is supplemented by a CPU design project that allows students to become proficient with Field Programmable Gate Array (FPGA) devices and associated CAD tools, as well as with GPU computing through nVidia CUDA or OpenCL languages.
(Lec: 3, Lab: 1, Tut: 0.25)
Requirements: Prerequisites: ELEC 252, ELEC 271, ELEC 274 or permission of the instructor Corequisites: Exclusions:   
Offering Term: W  
CEAB Units:    
Mathematics 0  
Natural Sciences 0  
Complementary Studies 0  
Engineering Science 28  
Engineering Design 23  
Offering Faculty: Smith Engineering  

Course Learning Outcomes:

  1. Write the behavioral and structural description of combinational and sequential circuits using Verilog or VHDL .
  2. Describe the internal organization and the logical/timing interface of various memory subsystems including asynchronous/synchronous static, dynamic, and flash memory, as well as understand computer bus protocols and I/O interfaces.
  3. Describe the concepts of data-level parallelism, CUDA/OpenCL kernel functions and threading for GPU architectures.
  4. Analyze/design testable combinational and sequential circuits using techniques such as D-algorithm, Design for Testability (DFT), Built-In-Self-Test (BIST) and Boundary-Scan Architecture.
  5. Analyze/design various high-performance digital circuits for fixed-point and floating-point arithmetic operations such as array multipliers, Booth algorithm, array dividers and multiplicative division, etc.
  6. Analyze/design race-free asynchronous sequential circuits using the flow table, merger diagram and transition diagram.
  7. Design, simulate, implement, and verify the datapath and control unit of a processor using Verilog/VHDL, with/without schematic design.
  8. Effectively communicate the outcome of the lab CPU design team project through a final report and design documentation.